The present invention relates to a semiconductor integrated circuit and a process for producing the same. More specifically, the invention relates to a method of device isolation which is adapted to improving the controllability of the threshold voltage of fine MOS transistors and to improving the junction breakdown voltage.
A selective oxidation method called LOCO (local oxidation of silicon)or trench isolation has heretofore been used for isolating devices in the semiconductor integrated circuits. According to this method, impurities that serve as a channel stop are uniformly doped (concentrated) under a thick insulating film (SiO.sub.2 film) that is formed in the isolation area. As disclosed in Japanese Patent Laid-Open No. 89940/1985, furthermore, there has been proposed the isolation of devices based on the selective oxidation by introducing impurity ions in amounts that vary depending on the sizes of isolation areas.
According to the above prior art, no attention has been given to the fact that the impurities doped in the isolation area are also diffused into the active area (area where the transistors are formed) when a thick insulating film is formed by selectively oxidizing the silicon substrate. As the active region becomes fine, furthermore, the threshold voltage of MOS transistors formed in the region becomes high, and the controllability for the threshold voltage decreases.